1. Field of the Invention
The invention relates in general to a method for checking an IC layout, and more particularly to a method for checking a wire layout causing high power wire resistance in the IC layout.
2. Description of the Related Art
FIG. 1 is a partially equivalent circuit diagram showing a conventional integrated circuit (IC). Referring to FIG. 1, the equivalent circuit 10 includes a voltage source 11, a plurality of equivalent wire resistors R11, R12, R13, R21, R22 and R23, and a plurality of device units 12, 13 and 14. Theoretically, the equivalent resistance of an ideal wire is zero in the circuit property. In fact, however, each wire has an equivalent resistance. If the electric currents flowing through the device units 12, 13 and 14 are I1, I2 and I3, respectively, because the equivalent wire resistors R21, R12 and R13 cause voltage drops and the equivalent wire resistors R21, R22 and R23 cause ground bounces, the voltages VG3 and V′G3 are represented in the following equations according to the ohm's law:VG3=V−R11(I1+I2+I3)−R12(I2+I3)−R13*I3  (1), andV′G3=R21(I1+I2+I3)+R22(I2+I3)+R23*I3  (2).
Thus, the operation voltage (the voltage drop across two ends) of the device unit 14 is not the ideal voltage (VDD-GND), but is (VG3-V′G3) which is less than (VDD-GND) for (R21+R11)(I1+I2+I3)+(R22+R12)(I2+I3)+(R23+R13)*I3. Hence, the larger the equivalent wire resistance is, the larger the voltage drop is. The large equivalent wire resistance may cause the timing problems and the functional failures of the device unit. The above-mentioned problem becomes worse when the IC manufacturing technology is getting more and more advanced such that the line width is getting smaller and smaller, and the wire's equivalent resistance is getting larger and larger. Thus, the difference between the actual operation voltage of the device and the ideal operation voltage thereof is getting larger and larger.
Consequently, it is an important subject of the circuit layout to effectively reduce the wire's resistance.
However, when the IC layout is done according to the currently used IC CAD (computer aided design) software, there are no known objective and effective rules and methods to judge whether or not the circuit layout causes the wire resistance too high. Instead, the circuit layout engineer can only check the complicated circuit layout with his/her naked eyes according to his/her experience for the subjective assertion. Thus, the prior art method is time-consuming, laborious, inefficient, and ineffective.